With conventional non-volatile memories, a known cell write technique is that of applying, to the cell drain terminal, a voltage having a moderately high value (e.g., 6.5 Volts), while a higher voltage value (e.g., 10.5 Volts) is applied to its gate.
To erase a cell, on the other hand, a high voltage (e.g., 10.5 Volts) is applied to the source terminal of the cell, while its control gate terminal is held at ground potential.
Such erasing is usually carried out simultaneously on all the cells of a device or all the cells in a memory block ("erasing by sectors").
All the high-voltage references needed for proper operation of a memory are conveniently generated, moreover, within the device from the standard external supply voltage (5 Volts). It should not be overlooked, however, that during the erasing phase, current flow occurs between the cell sources and the substrate; while this is quite small (about 1 .mu.A) for an individual cell, the overall current would be fairly high in the instance of a large storage capacity device, making it difficult to provide a voltage booster within the integrated circuit which can drive the source electrodes during that operation phase. Furthermore, the application of a high reverse bias between the cell sources and the substrate may introduce reliability problems in that voltages close to the junction breakdown voltage may be reached and hot holes may be generated which become trapped at or within the gate dielectric (e.g., an oxide).
It is for the above-outlined reasons that an alternative memory erasing technique has been developed whereby the source electrodes of the cells are held at a relatively low positive voltage (e.g., 5 Volts), while a negative voltage of adequate value (approximately -10.5 Volts) is applied to the gate electrodes. The circuit which generates this voltage is not required to supply a large current, so that it can be provided internal to the integrated storage circuit.
Thus, in more recently developed storage cell devices--such as "flash" devices--implemented with field-effect transistors, a high positive or negative voltage, relative to a reference potential, is applied at the programming stage to the gate terminal of each storage cell, depending respectively on whether the involved phase is a write or an erase phase.
In circuit solutions currently in use to implement that technique, the positive or negative boosted voltages for driving the storage cells during the write and erase phases are applied to the gate terminals through suitable selection transistors with switch functions. However, driving the storage cells through their gate terminals poses a major problem from the wide variation in value of the voltages and their polarities.
A variation of 21 Volts, at the above-mentioned voltage values, would require use of "high-voltage" transistors and incorporation of a number of circuit configurations to prevent undesired leakage or breakdown of parasitic diodes in the integrated circuit.
Also, due to problems from charge injection, selection transistors cannot be used where a single-well integration process in CMOS technology is employed.